A Defect-tolerant Cluster in a Mesh SRAM-based FPGA

International audienceIn this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input combinations. While at the interconnect level, fine grain redundancy is introduced which not only bypasses defects but also increases routability. Taking advantage of the sparse intra-cluster interconnect structures, routability is further improved by efficient distribution of feedback paths allowing more flexibility in the connections among logic blocks. Emulation results show a significant improvement of about 15% and 34% in the robustness of logic block and intra-cluster interconnect respectively. Furthermore, the impact of these hardening schemes on the testability of the FPGA cluster for manufacturing defects is also investigated in terms of maximum achievable fault coverage and the respective cost

Outils de placement et de routage pour des architectures FPGA sécurisées contre les attaques DPA

La logique différentielle WDDL permet de protéger les circuits cryptographiques contre les attaques par analyse différentielle de la consommation de courant. Néanmoins, pour qu'elle soit efficace, il faut que le routage des signaux différentiels du circuit soit équilibré. Cette thèse s'intéresse au problème d'équilibre des signaux duaux d'un circuit implémenté en logique WDDL sur des architectures FPGA. D'abord, nous nous intéressons à une architecture FPGA hiérarchique arborescente, appelée MFPGA. Nous proposons des méthodes de partitionnement et de placement des cellules logiques, et nous élaborons un algorithme de routage Timing-Balance-Driven, dans le but d'équilibrer le routage des signaux duaux en termes de temps de propagation. Ensuite, nous adaptons les précédentes techniques à l'architecture matricielle. Par ailleurs, nous proposons une approche de routage différentiel pour une architecture matricielle à base de clusters. Dans un troisième temps, nous proposons un nouvel algorithme de routage Timing-Balance-Driven indépendant de l'architecture, et nous montrons son efficacité dans les architectures MFPGA et matricielle. Nous remarquons que le déséquilibre restant dans l'architecture MFPGA est dû au déséquilibre entre les longueurs des segments de routage.PARIS-BIUSJ-Mathématiques rech (751052111) / SudocSudocFranceF

Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA

International audienceCryptographic devices are vulnerable to Differential Power Attacks (DPA). To resist these attacks, the Wave Dynamic Differential Logic (WDDL) has been proposed. However, the limitation of this technique is that it requires balanced routing of the dual rail interconnect between gates, to obtain equal propagation delays and power consumption on differential signals. This paper addresses the problem of routing balance in Mesh FPGA. First, we perform a dual placement in cluster based Mesh FPGA. Then, we propose a differential routing method which achieves a perfectly balanced routed signals in terms of wire length and switch number

Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-railsignals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing

International audienceIn this paper, we propose placement and routing techniques to deal with the timing unbalance problem in wave dynamic differential logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results demonstrate that our placement and routing techniques reduce the delay unbalance significantly. They achieve 93% of average timing balancing improvement in WDDL designs

Efficient Tree Topology for FPGA Interconnect Network

International audienceThis paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butter y-Fat-Tree topology, and an upward network using hierarchy. Studies based on Rent's Rule show that switch requirements in this architecture grow slower than in traditional Mesh topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results show that the Tree-based architecture can implement MCNC benchmark circuits with an average gain of 54% in total area compared with Mesh architecture

Placement and Routing Techniques to Improve Delay Balance of WDDL Netlist in MFPGA

International audienceThe Wave Dynamic Differential Logic (WDDL) is a promising countermeasure to protect cryptographic devices from Differential Power Attacks (DPA). But the key challenge is to maintain symmetry between dual networks, so as to obtain equal propagation delays and power consumption on differential signals. In this paper, we deal with the problem of timing unbalance. We study the impact of different placement strategies on the delay unbalance in a Tree-based FPGA. In addition, we present a new timing-balance driven router which is based on the Pathfinder routing algorithm. Our placement and routing tools improve significantly the delay balance. In fact, the results obtained with WDDL DES netlist show that the average delay unbalance was reduced by 90%

Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA

International audienceAn application specific inflexible FPGA (ASIF) is an FPGA with reduced flexibility and improved density. An ASIF is reduced from an FPGA for a predefined set of applications that operate at mutually exclusive times. This work presents a new tree-based ASIF and uses a set of 16 MCNC benchmarks to explore the effect of lookup table (LUT) and arity size on it and results are then compared with those of mesh-based ASIF. For tree-based ASIF, LUT size is varied from 3 to 7 while arity size is varied from 4 to 8 and 16. Experimental results show that smaller LUTs with higher arity sizes produce good area results but poor performance results. Finally experimental results show that LUT 4 with arity 16 gives best area-delay product and compared to mesh-based ASIF, this combination gives 12% routing area gain

Lichenoid lesions around the anus: An unusual site of Hailey–Hailey disease

Abstract The anal region is an unusual site of Hailey–Hailey disease. It manifests with lichenoid lesions with crusted erosions around the anus. It should be differentiated from condylomata acuminata, extramammary Paget disease, and bowenoid papulosis